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- W1514444429 abstract "The Post Office is an asynchronous, 300,000 transistor, full-custom CMOS chip designed as the communication coprocessor for the Mayfly scalable parallel processor. Since communication latency is a critical system performance factor, the Post Office had to be designed both for high speed operation, and to function in machine configurations containing widely varying numbers of processing elements. Performance and functional requirements led to the development of a new asynchronous design style called burst-mode. The Post Office complexity forced us to develop a set of synthesis tools to support this design style. The paper provides a case study of this design experience, including a description of the Post Office behavior and its architecture, the design style that we employed, a brief description of our tools, and a retrospective view of the design process." @default.
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- W1514444429 date "1993-10-01" @default.
- W1514444429 modified "2023-10-06" @default.
- W1514444429 title "The Post Office experience: designing a large asynchronous chip" @default.
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- W1514444429 doi "https://doi.org/10.1016/0167-9260(93)90036-c" @default.
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