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- W1517366489 abstract "Recently, studies of acceleration of software operations on a processor have been executed aggressively using Field Programmable Gate Arrays (FPGAs). However, currently available FPGA architecture presents waste under a parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous parts of configuration memory. This paper therefore presents a proposal for a parallel-operation-oriented FPGA architecture including a shared common configuration memory. In this research, a parallel-operation-oriented FPGA with four programmable gate arrays sharing a common configuration memory has been designed using a 0.18 μm CMOS process technology. The advantage of the parallel-operation-oriented FPGA is clarified and a design technique to achieve a high-performance parallel-operation-oriented FPGA is discussed." @default.
- W1517366489 created "2016-06-24" @default.
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- W1517366489 date "2015-05-01" @default.
- W1517366489 modified "2023-09-26" @default.
- W1517366489 title "Design of a parallel-operation-oriented FPGA" @default.
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- W1517366489 doi "https://doi.org/10.1109/isne.2015.7132021" @default.
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