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• W1519191507 abstract "We report a Planar Stack Technology (PST) suitable for scaling and combining DRAM with logic circuits. Key features of PST technology are retrograde twin well, shallow trench isolation (STI), self-aligned poly plug structure, damascene W bit-line, Ta/sub 2/O/sub 5/ capacitor dielectric and planarized capacitor formation. This new architecture provides planar surfaces for all the lithographic steps and is easy to combine CMP-based backend processes. Although the process margin and electrical performance are proven using full density, 256 M DRAM chip, this technology can be applied to 1 G bit DRAM and beyond with simple photo lithographic scaling." @default.
• W1519191507 created "2016-06-24" @default.
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• W1519191507 date "2002-12-24" @default.
• W1519191507 modified "2023-09-27" @default.
• W1519191507 title "A new planar stacked technology (PST) for scaled and embedded DRAMs" @default.
• W1519191507 doi "https://doi.org/10.1109/iedm.1996.554054" @default.
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