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- W1520359979 abstract "A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO has been introduced. The VCO has a centre oscillating frequency of about 7.5 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at the bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at the supply voltage of -5 V." @default.
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- W1520359979 date "1993-09-01" @default.
- W1520359979 modified "2023-09-24" @default.
- W1520359979 title "7.5 Gb/s Monolithically Integrated Clock Recovery using PLL and 0.3 μM Gate Length Quantum Well HEMTs" @default.
- W1520359979 doi "https://doi.org/10.18419/opus-8204" @default.
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