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- W1520407833 abstract "DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell- induced memory errors at the system level. Although the availability of weak cell location information can be leveraged to maximize the weak-cell-induced error tolerance, a straightforward realization of weak cell aware error tolerance tends to suffer from significant memory access latency overhead, especially in the presence of a large number of weak cells. This paper presents a design solution that can realize weak cell aware error tolerance at very small memory access latency overhead. The key is to use a hybrid error detection/correction process to eliminate unnecessary access to the weak cell location information. We carried out extensive simulations and evaluations to demonstrate the effectiveness of this design solution and the trade-offs. Beyond theoretical analysis on the latency overhead, we further performed full-system simulations based upon a cycle-accurate x86 simulator and DRAM simulation, and implemented our design solution using an FPGA development board with on-board DRAM chips. The results successfully show that our design solution can readily handle the weak-cell-induced memory error rate of upto 10−4∼ 10−3 at very small (even negligible) latency overhead." @default.
- W1520407833 created "2016-06-24" @default.
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- W1520407833 date "2015-05-01" @default.
- W1520407833 modified "2023-09-27" @default.
- W1520407833 title "Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes" @default.
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- W1520407833 doi "https://doi.org/10.1109/imw.2015.7150283" @default.
- W1520407833 hasPublicationYear "2015" @default.
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