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- W1520465974 abstract "This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. The total power consumption of the 3-tap DFE is 27mW under 1V, achieving 0.67 pJ/bit energy efficiency." @default.
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- W1520465974 date "2015-06-01" @default.
- W1520465974 modified "2023-09-24" @default.
- W1520465974 title "A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS" @default.
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- W1520465974 doi "https://doi.org/10.1109/newcas.2015.7182113" @default.
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