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- W1520749062 abstract "In this chapter, electronic design automation (EDA) techniques and methods for electrostatic discharge, electrical overstress (EOS), and latchup are discussed. Design rule checking (DRC), layout-versus-schematic (LVS), and electrical rule check (ERC) methods are used for electrostatic discharge (ESD), latchup, and EOS checking and verification. As time progresses, ESD computer-aided design (CAD) methods are being propagated to EOS CAD methods, to address ESD and EOS in the same design tool. The example of Calibre PERCTM shows how the methods of ESD are being extended to the EOS issue. A key issue is the checking and verification of analog-to-digital cross-domain sign lines." @default.
- W1520749062 created "2016-06-24" @default.
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- W1520749062 date "2014-08-11" @default.
- W1520749062 modified "2023-09-27" @default.
- W1520749062 title "Analog ESD and Latchup Design Rule Checking and Verification" @default.
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- W1520749062 doi "https://doi.org/10.1002/9781118701409.ch12" @default.
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