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• W1520972637 abstract "In this dissertation, we address the design of multi-functional arithmetic units working with the most common fixed-point number representations, namely: unsigned, sign-magnitude, fractional, ten's and two's complement notations. The main design goal is to collapse multiple complex arithmetic operations into a single, universal arithmetic unit, aiming at the highest possible reutilization of shared hardware resources. More specifically, we propose an Arithmetic unit for collapsed Sum-of-Absolute Differences (SAD) and Multiplication operations (AUSM). This unit collapses various multi-operand addition based operations, such as SAD, universal notation multiplication, Multiply-Accumulate (MAC), fractional multiplication. Our AUSM design demonstrated high hardware reutilization level of up to 75%, yet its performance is comparable to the fastest related stand-alone designs supporting the individual operations. Another complex arithmetic operation, considered in this thesis is Matrix-Vector Multiplication. We collapsed fixed-point dense and sparse matrix-vector multiplication in one unit. It's Xilinx Virtex II Pro implementation suggests up to 21GOPS on a xc2vp100-6 FPGA device. Furthermore, in this thesis, we propose an arithmetic unit for universal addition, which supports addition/subtraction in binary and Binary Coded Decimal (BCD) representations in various sign notations. The hardware reutilization level for this unit was 40% and its performance was estimated to be more than 82MOPS. All considered units require massively parallel memory organizations, capable of providing high data throughput. Therefore, in this thesis, we propose a high-performance address generator (AGEN) employing a modified version of the low-order interleaved memory access approach. Our experiments suggest that the AGEN can produce 8 X 32 - bit addresses every 6 ns. Overall, in this dissertation, we demonstrated a design approach, which allows collapsing of multiple arithmetic operations into performance efficient universal designs with high level of hardware reutilization among the implemented functions." @default.
• W1520972637 created "2016-06-24" @default.
• W1520972637 creator A5050305384 @default.
• W1520972637 date "2007-11-27" @default.
• W1520972637 modified "2023-09-23" @default.
• W1520972637 title "Arithmetic soft-core accelerators" @default.
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