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- W1520991006 abstract "This paper presents a design technique for high fidelity multistage decimation filters based on polyphase and decimator structures, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 15 resolution. The resulting filter coefficients are constrained to the required length using a bit flipping algorithm. This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to other approximation methods. The coefficients and frequency responses of the cascaded filter are reported. >" @default.
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- W1520991006 date "2002-12-17" @default.
- W1520991006 modified "2023-09-26" @default.
- W1520991006 title "A design technique for polyphase decimators with binary constrained coefficients for high resolution A/D converters" @default.
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- W1520991006 doi "https://doi.org/10.1109/iscas.1994.409043" @default.
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