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- W1523096050 abstract "A 2-D electronic analogue simulator circuit is introduced to model the latch-up vulnerability in CMOS circuits. The simulator is applied to analyze the relative radiation hardness as a function of circuit layout and distribution of substrate contacts. The results of simulations show good agreement with elsewhere obtained experimental flash X-ray results on similar structures." @default.
- W1523096050 created "2016-06-24" @default.
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- W1523096050 date "2005-08-25" @default.
- W1523096050 modified "2023-09-25" @default.
- W1523096050 title "Electronic circuit analogue model for CMOS devices" @default.
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- W1523096050 doi "https://doi.org/10.1109/radecs.2001.1159291" @default.
- W1523096050 hasPublicationYear "2005" @default.
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