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- W1523449622 abstract "A novel approach to build a full-adder circuit is presented using the modified binary tree. In this approach, the full adder can take only 15 transistors. In the residue-number-system-based digital signal processing architectures, look-up tables are an important computational element. Using the modified binary tree, an efficient row/column decoder is proposed for the look-up table implementation. It is observed that the look-up table based on the conventional approach occupies 26% more area and takes 1.5 ns more access time than the look-up table based on the modified binary tree. >" @default.
- W1523449622 created "2016-06-24" @default.
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- W1523449622 date "2002-12-09" @default.
- W1523449622 modified "2023-09-23" @default.
- W1523449622 title "Implementation of high-performance and highly efficient computational modules using binary tree structures at the device level" @default.
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- W1523449622 doi "https://doi.org/10.1109/mwscas.1991.252078" @default.
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