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• W1524563994 abstract "CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and an increase in threshold voltage by 18% are directly proportional to an increase in channel resistance, thereby substantially increasing the NAND gate circuit timing delay." @default.
• W1524563994 created "2016-06-24" @default.
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• W1524563994 date "2006-03-30" @default.
• W1524563994 modified "2023-09-23" @default.
• W1524563994 title "Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics" @default.
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• W1524563994 doi "https://doi.org/10.1109/irws.2005.1609564" @default.
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