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- W1524791468 abstract "Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combinational logic chains and investigate techniques to increase circuit robustness in terms of decreasing the probability of upsetting the capturing latch given a particle strike. We show that using a technique of inserting simple cross-coupled inverter pairs on error prone sites, as well as intelligently placing lower V/sub th/ devices and readjusting device width, can increase the robustness by nearly 20% thereby increasing the mean time between soft errors by almost 25%. This technique incurs substantially less overhead than traditional redundancy approaches to mitigating soft errors." @default.
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- W1524791468 date "2005-03-31" @default.
- W1524791468 modified "2023-09-27" @default.
- W1524791468 title "Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate" @default.
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- W1524791468 doi "https://doi.org/10.1109/isqed.2005.61" @default.
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