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- W1527793361 abstract "The specifications for a 1-GOPS CMOS programmable video signal processor are presented. To perform the specified functions using a single chip, four macro blocks, each including a fourth-order inner-product circuit, a shift register with switches, a barrel shifter, and a nonlinear mapper (limiter) are used. The adders are provided at the multiplier input for a symmetric FIR (finite impulse response) filter. The macro blocks have the same configuration, and their function can be programmed externally. The blocks are connected to form a systolic array. A carry-ripple adder, which is usually the critical path of both a multiplier and an adder, is not used in this circuit. The layout of the LSI was generated by an automatic layout program. The sixteen multiplier-adders integrated in the chip are sufficient for most standard applications. It is expected that the LSI will be used for digital video equipment for conventional TV, high-definition television systems, and computer vision equipment. >" @default.
- W1527793361 created "2016-06-24" @default.
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- W1527793361 date "2003-01-13" @default.
- W1527793361 modified "2023-09-27" @default.
- W1527793361 title "A 1-GOPS CMOS programmable video signal processor" @default.
- W1527793361 cites W2316111874 @default.
- W1527793361 doi "https://doi.org/10.1109/isscc.1989.48243" @default.
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