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• W1528425101 abstract "In this paper, we present a 65 nm CMOS technology for high performance SoC (system-on-chip), especially for broadband core chip applications. Logic gate length is scaled down to 30 nm, and embedded SRAM cell size is shrunk to 0.6 /spl mu/m/sup 2/. Embedded DRAM cell size is 0.11 /spl mu/m/sup 2/. MOSFET's in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics to suppress gate leakage current. Furthermore poly-SiGe gate electrode and Ni Salicide were adopted to control high gate electrode activation and USJ (ultra shallow junctions) under low thermal budget. Hi-NA193-nm lithography with alternating phase shift mask and the slimming process combined with non-slimming trim mask process were employed to achieve a small SRAM cell. Cu interconnects; using low-k dielectrics has an 180 nm pitch." @default.
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• W1528425101 date "2003-06-26" @default.
• W1528425101 modified "2023-10-18" @default.
• W1528425101 title "65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications" @default.
• W1528425101 doi "https://doi.org/10.1109/iedm.2002.1175778" @default.
• W1528425101 hasPublicationYear "2003" @default.
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