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- W1531378670 abstract "This paper proposes a dynamic delayed line bus scheme (DDL) for low-power on-chip buses. This scheme dynamically introduces a delay to bus lines having a certain switching activity to create relative delay between opposite switching adjacent lines. The optimum relative delay introduced by this proposed scheme is shown to reduce the power dissipation by up to 16%." @default.
- W1531378670 created "2016-06-24" @default.
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- W1531378670 date "2004-12-23" @default.
- W1531378670 modified "2023-09-23" @default.
- W1531378670 title "Low-power on-chip bus architecture using dynamic relative delays" @default.
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- W1531378670 doi "https://doi.org/10.1109/socc.2004.1362419" @default.
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