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- W1540248841 abstract "Packet classification is a key network function enabling a variety of network applications, such as network security, Quality of Service (QoS) routing, and other value-added services. Routers perform packet classification based on a predefined rule set. Packet classification faces two challenges: (1) the data rate of the network traffic keeps increasing, and (2) the size of the rule sets are becoming very large. In this paper, we propose an FPGA-based packet classification engine for large rule sets. We present a decomposition-based approach, where each field of the packet header is searched separately. Then we merge the partial search results from all the fields using a merging network. Experimental results show that our design can achieve a throughput of 147 Million Packets Per Second (MPPS), while supporting upto 256K rules on a state-of-the-art FPGA. Compared to the prior works on FPGA or multi-core processors, our design demonstrates significant performance improvements." @default.
- W1540248841 created "2016-06-24" @default.
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- W1540248841 date "2015-07-01" @default.
- W1540248841 modified "2023-09-25" @default.
- W1540248841 title "Large-scale packet classification on FPGA" @default.
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- W1540248841 doi "https://doi.org/10.1109/asap.2015.7245738" @default.
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