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- W1544857552 abstract "A parametric packed-switched scalable network on chip allows energy/throughput/latency tradeoff for data-intensive communication-centric systems. At a clock rate of 200MHz the network guarantees block-free average 1 Gb/s per channel. The test chip includes 64-interfaces network on chip and traffic generators." @default.
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- W1544857552 date "2004-12-23" @default.
- W1544857552 modified "2023-09-25" @default.
- W1544857552 title "A 0.13um 1Gb/s/channel store-and-forward network on-chip" @default.
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- W1544857552 doi "https://doi.org/10.1109/socc.2004.1362381" @default.
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