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- W1545447777 abstract "The development of micro-electronics in the last few years is increasingly spectacular. This success mainly results from an increasingly thorough know-how and a technological master ship asset thanks to the new software. Transistor MOS is at the same time the principal actor and the vector of this technological development [1]. The constant reduction of the MOS transistors dimensions, notably the length of their channel and the oxide thickness, lead the apparition of parasitic phenomena [2]. This later corresponds to a modification of the threshold voltage and the preponderance of the short channel effects that damages the electric features of the MOS transistor [3]. In this paper, we expose firstly the main technological process of an ultimate MOS transistor. We consider, a 0.35μm technology, simulated by the technological module “DIOS” of the ISE-TCAD (Integrated Systems Engineering – Technology Computer Aided Design) environment [4]. Then, we present the result of the electrical simulation. We use in this case the module “DESSIS” of the same sofware ISE-TCAD in order to observe the influence of the technological parameters and especially the effect of the oxide thickness (2.4 10nm), the length of the gate (0.180.5μm) and the channel doping (3.7e173.5e18cm ) on the behaviour of the MOS transistor, notably on the threshold voltage evolution VT." @default.
- W1545447777 created "2016-06-24" @default.
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- W1545447777 date "2009-03-29" @default.
- W1545447777 modified "2023-10-18" @default.
- W1545447777 title "ON THE THRESHOLD VOLTAGE EVOLUTION FOR SUBMICRONIC MOS TRANSISTORS" @default.
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