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• W1547009104 abstract "An electrically erasable, reprogrammable, 90-ns 1-Mb flash memory capable of greater than 100000 erase/program cycles is described. The memory implements a command port and an internal reference voltage generator, allowing microprocessor-controlled reprogramming. The 90-ns access time results from the 95- mu A memory cell current, low resistance polysilicide word lines, advanced scaled periphery transistors, and a di/dt optimized data-out buffer. Using CMOS inputs, power dissipation is 40 mW in the active state and 20 mu W in standby. The memory electrically erases in 900 ms and programs at the rate of 10 mu s/byte. The device contains thirty-two columns of redundant elements and utilizes flash memory cells to store the address of repaired columns. The memory was fabricated on a 1- mu m double-poly n-well CMOS process. A typical cell erase/program V/sub t/ margin is shown as a function of the number of reprogramming cycles. After 100000 cycles there is still a 2.5-V program-read margin to ensure data retention. Device parameters are listed. >" @default.
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• W1547009104 date "2003-01-13" @default.
• W1547009104 modified "2023-09-27" @default.
• W1547009104 title "A 90 ns 100 K erase/program cycle megabit flash memory" @default.
• W1547009104 cites W2049849269 @default.
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• W1547009104 doi "https://doi.org/10.1109/isscc.1989.48233" @default.
• W1547009104 hasPublicationYear "2003" @default.
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