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- W1551158365 abstract "A 128×8b CMOS SRAM with TTL input/output levels will be presented. The SRAM has been fabricated in a 1.0μm double-poly silicon double-metal CMOS technology Chip size is 8×13.65mm. Typical standby current is 5μA with 100mW dissipatlon at 10MHz. Noise immunity has been achieved from a dual threshold level data transfer." @default.
- W1551158365 created "2016-06-24" @default.
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- W1551158365 date "2005-03-23" @default.
- W1551158365 modified "2023-09-25" @default.
- W1551158365 title "A 35ns 1Mb CMOS SRAM" @default.
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- W1551158365 doi "https://doi.org/10.1109/isscc.1987.1157110" @default.
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