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- W1551656289 abstract "The gate length of a few tens of a nanometer for CMOS has become a distinct possibility due to technology scaling. Furthermore, the amount of transistors in a single die is increasing steadily over time towards gigascale integration (GSI) level. This development creates a noise and power dissipation problems into a system design. In addition to this, signaling over nanometer interconnects represents a major bottleneck in ULSI systems due to the dominant limitation of signal propagation delays. To a large extent, the on-chip signaling technique determines the reliability, speed, and power consumption of a network-on-chip (NoC). An efficient on-chip signaling scheme is the one that maximizes the data rate per pin, minimizes power dissipation, and provides good noise immunity. Such signaling convention can dramatically increase available data rate and hence system performance. Three signaling techniques, namely voltageand current-mode differential signaling and simultaneous current-mode bidirectional signaling, were selected from the on-chip signaling scheme, which has a promising feature for the future technology scaling impact as a case study. Interconnects were modeled using transmission line model from Spectre and lumped RC-model. For the latter, the length of the interconnect varied from 0.1 mm to 3 mm. Finally, a 32-bit bus was constructed by utilizing the above mention techniques. Simulation and performance analysis was carried out for 0.18 μm technology." @default.
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- W1551656289 date "2004-01-01" @default.
- W1551656289 modified "2023-09-23" @default.
- W1551656289 title "Signaling Techniques for NoC" @default.
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