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- W1554849232 abstract "Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior." @default.
- W1554849232 created "2016-06-24" @default.
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- W1554849232 date "2002-01-01" @default.
- W1554849232 modified "2023-09-27" @default.
- W1554849232 title "Extracting Exact Time Bounds from Logical Proofs" @default.
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- W1554849232 doi "https://doi.org/10.1007/3-540-45607-4_14" @default.
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