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• W1554854833 abstract "This paper reports the design of an on-chip Test Pattern Generator (TPG) for VLSI circuits that avoids generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random quality of the test patterns generated while ensuring fault coverage close to the figures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR/CA. The theoretical framework of CA has provided the foundation of this work. A GA based evolution scheme is employed to achieve the desired TPG developed over the theory of cellular automata." @default.
• W1554854833 created "2016-06-24" @default.
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• W1554854833 date "2003-06-26" @default.
• W1554854833 modified "2023-09-27" @default.
• W1554854833 title "An evolutionary strategy to design an on-chip test pattern generator without prohibited pattern set (PPS)" @default.
• W1554854833 cites W2097890209 @default.
• W1554854833 doi "https://doi.org/10.1109/ats.2002.1181721" @default.
• W1554854833 hasPublicationYear "2003" @default.
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