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• W1556528025 startingPage "831" @default.
• W1556528025 abstract "A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25-μm CMOS prototype dissipates 140 mW and occupies an active area of 5 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . At 40 megasamples/s (40 MS/s), the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB." @default.
• W1556528025 created "2016-06-24" @default.
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• W1556528025 date "2015-09-01" @default.
• W1556528025 modified "2023-09-25" @default.
• W1556528025 title "An Integrator-Based Pipelined ADC With Digital Calibration" @default.
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• W1556528025 doi "https://doi.org/10.1109/tcsii.2015.2435514" @default.
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