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- W1556881604 abstract "Gate-array designs normally require larger chip area than equivalent standard-cell designs. However, as netlists get larger routing becomes more important. In this paper, standard-cell channel routing is used to reduce the chip area of a specially designed 0.8 mu m gate-array architecture. For very large netlists, results show that gate-array designs can have equal chip area and performance to standard-cell designs. >" @default.
- W1556881604 created "2016-06-24" @default.
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- W1556881604 date "2003-01-02" @default.
- W1556881604 modified "2023-09-25" @default.
- W1556881604 title "Using standard-cell design methodologies on a gate-array base" @default.
- W1556881604 doi "https://doi.org/10.1109/euasic.1992.227989" @default.
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