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- W1557033289 abstract "The Field Programmable Gate Array (FPGA) routing resources are fixed and their usage is constrained by the location of Programmable Connections (PC's) such as antifuses. The routing or the interconnect delays are determined by the length of segments assigned to the nets of various lengths and the number of PC's programmed for routing of each net. Due to the use of PC's certain unconventional faults may appear. This paper models the PC faults and analyzes the performance of FPGA channel architecture under faulty conditions to achieve 100% routability with graceful degradation in performance. A channel architecture has been synthesized to achieve routability and performance even under faulty conditions. Results on a set of industrial designs and MCNC benchmark examples show the feasibility of achieving routability and performance under a large number of faults in the channel." @default.
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- W1557033289 date "1994-01-01" @default.
- W1557033289 modified "2023-09-23" @default.
- W1557033289 title "On channel architecture and routability for FPGA's under faulty conditions" @default.
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- W1557033289 doi "https://doi.org/10.1007/3-540-58419-6_121" @default.
- W1557033289 hasPublicationYear "1994" @default.
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