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• W1557770645 abstract "An advanced bipolar-process integration technology was developed and used for fabricating a 6-/spl mu/m/sup 2/-cell-size transistor with high cut-off frequency of 40 GHz. This process uses 0.25-/spl mu/m lithography technology and shallow and deep trench isolations for reducing parasitic capacitance. ECL circuit performance is consequently improved up to 25 ps. A combination of low-energy ion-implantation and two-step base annealing was applied to form a low-leakage and shallow base junction. This technology was applied to an ultra-fast logic LSI, so we confirmed that the 0.25-/spl mu/m technology can provide bipolar transistors with sufficient performance for use in ULSIs." @default.
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• W1557770645 date "2002-11-27" @default.
• W1557770645 modified "2023-09-24" @default.
• W1557770645 title "A 6-μm/sup 2/ bipolar transistor using 0.25-μm process technology for high-speed applications" @default.
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• W1557770645 doi "https://doi.org/10.1109/bipol.1998.741911" @default.
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