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- W1559984937 abstract "The inter-chip delay penalty for hybrid-WSI and MCM designs is much lower than that for printed wiring boards. Consequently, the system partitioning and die size optimization problems must be attacked using a different set of parameters. This paper develops a new figure of merit for optimal HWSI/MCM chip sizing based upon system quality level, cost, and silicon efficiency. The figure of merit is then applied to a 500k gate MCM case study. >" @default.
- W1559984937 created "2016-06-24" @default.
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- W1559984937 date "2002-12-17" @default.
- W1559984937 modified "2023-09-23" @default.
- W1559984937 title "Optimal chip sizing for hybrid-WSI" @default.
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- W1559984937 doi "https://doi.org/10.1109/icwsi.1994.291231" @default.
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