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- W1561441105 abstract "This paper proposes a methodology for the development of simple arithmetic self-checking circuits using a signed digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of signed digit representation, allowing carry-free operations. In a carry free adder, the parity can be easily checked, allowing therefore detecting the occurrence of a fault belonging to the considered stuck-at fault set. The proposed architecture is therefore very suitable for the implementation of self-checking adders that are also fast due to the same carry free property." @default.
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- W1561441105 date "2004-03-02" @default.
- W1561441105 modified "2023-09-25" @default.
- W1561441105 title "Error detection in signed digit arithmetic circuit with parity checker [adder example]" @default.
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- W1561441105 doi "https://doi.org/10.1109/dftvs.2003.1250137" @default.
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