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• W1563576744 abstract "This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm/sup 2/ and a SRAM memory density of 1.4 Mb/mm/sup 2/ using a sub-0.49 /spl mu/m/sup 2/ bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described." @default.
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• W1563576744 date "2005-04-19" @default.
• W1563576744 modified "2023-10-17" @default.
• W1563576744 title "A 65 nm CMOS technology for mobile and digital signal processing applications" @default.
• W1563576744 cites W2029316851 @default.
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• W1563576744 doi "https://doi.org/10.1109/iedm.2004.1419255" @default.
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