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- W1565970025 abstract "This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 μm CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLRE-UTRA of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR)." @default.
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- W1565970025 date "2015-08-01" @default.
- W1565970025 modified "2023-09-25" @default.
- W1565970025 title "A Highly Efficient CMOS Envelope Tracking Power Amplifier Using All Bias Node Controls" @default.
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- W1565970025 doi "https://doi.org/10.1109/lmwc.2015.2440652" @default.
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