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- W1566068888 abstract "This paper describes a design technique for multiplier-free FIR filters to be used as decimation stages in /spl Sigma//spl Delta/ converters. The proposed solution used right shifters and accumulators to implement power-of-two multiplications; moreover, it minimizes the number of right shifts in the whole filter, thus allowing high clock rate operation. The resulting architecture reduces the area requirement with respect to conventional multiplier-based solutions." @default.
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- W1566068888 date "2002-11-28" @default.
- W1566068888 modified "2023-09-27" @default.
- W1566068888 title "Efficient implementation of multiplier-free decimation filters for ΣΔ A/D conversion" @default.
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- W1566068888 doi "https://doi.org/10.1109/icecs.1998.814851" @default.
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