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- W1566076317 abstract "FPGA test cost can be greatly reduced by minimizing the number of test configurations. A test technique is presented for FPGAs with multiplexer-based routing architectures in which multiple logical paths through each multiplexer is enabled instead of only one path. It is shown that for Xilinx Virtex-II and Spartan-3 FPGAs only 8 test configurations are required to achieve 100% stuck-at, PIP stuck-on, and PIP stuck-off fault coverage." @default.
- W1566076317 created "2016-06-24" @default.
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- W1566076317 date "2005-02-22" @default.
- W1566076317 modified "2023-09-26" @default.
- W1566076317 title "Minimizing the number of test configurations for FPGAs" @default.
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- W1566076317 doi "https://doi.org/10.1109/iccad.2004.1382702" @default.
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