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• W1566358637 abstract "Summary form only given. Every new semiconductor technology node provides further miniaturization and higher performance, thus increasing the functions that electronic products could offer. Although adding such new functions do benefit the end-user, but they also necessitate finer and denser semiconductor fabrication processes, which make chips more susceptible to defects. Today, as nanometer technologies are reaching defect susceptibility levels that result in lowering the manufacturing yield and reliability, and hence lengthening the production ramp-up period, and therefore the time to volume (TTV). The impact on manufacturability and TTV is very critical for the semiconductor industry. It puts the conventional IC realization flow at an impasse. In fact, every single phase in the IC realization flow has an impact yield and reliability, including the design phase, prototyping, volume fabrication, test, assembly, packaging, failure analysis and even the post-production life cycle of the chip. In order to optimize yield and reach acceptable TTV levels, the semiconductor industry needs to adopt advanced manufacturability optimization solutions. These solutions need to be implemented at different phases of the chip realization flow. The conventional semiconductor manufacturing infrastructure, i.e. the external equipment and processes, alone are insufficient to handle such advanced solutions; supplemental on-chip infrastructure is needed. To optimize manufacturability, the industry has recently introduced a range of embedded intellectual-property (IP) blocks, called infrastructure IP. These are meant for inclusion into IC design and utilized during the different phases of product realization. Semiconductor IP is well known for the last decade. Most of the known IP blocks, though, are functional ones, such as embedded processor, memory, analog, or FPGA cores. Whereas, infrastructure IP (I-IP) is not functional, i.e. does not contribute to the normal functionality of a given IC. Rather, I-IP is embedded in an IC solely to ensure its manufacturability and lifetime reliability. This role is similar to the infrastructure elements of a building, such as wiring networks or plumbing, which are independent from the actual function of the building. This paper introduces the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such infrastructure IP. The paper discusses the yield optimization loops. And then, it concentrates on several examples of infrastructure IP for process monitoring, test & repair, debug & diagnosis, timing, and fault tolerance, while demonstrating their effectiveness in improving yield and reliability." @default.
• W1566358637 created "2016-06-24" @default.
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• W1566358637 date "2005-03-21" @default.
• W1566358637 modified "2023-09-25" @default.
• W1566358637 title "Optimizing SoC manufacturability" @default.
• W1566358637 doi "https://doi.org/10.1109/icvd.2005.133" @default.
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