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- W1566783014 abstract "The Electrostatic Discharge ESD power grid and metal interconnects have a significant impact on the (ESD) robustness of the semiconductor chip. In the ESD design synthesis of interconnects, there are two primary issues. With the design synthesis of the interconnects, the failure of the interconnect is critical to the determination of the interconnect minimum requirements. In ESD design synthesis, guidelines and ground rules are needed to identify the proper wire width and via number based on the ESD objective. The power grid resistance is critical to the ability of the semiconductor current to discharge the current to the power rail bond pads. This chapter highlights some of the power grid considerations for Charged Device Model (CDM), IEC 61000-4-2, and Human Metal Model (HMM) specifications. ESD design rule checking (DRC) and verification methodologies can be used to avoid ESD failures. Controlled Vocabulary Terms electrostatic discharge; power grids; semiconductor devices; wires (electric)" @default.
- W1566783014 created "2016-06-24" @default.
- W1566783014 creator A5028723740 @default.
- W1566783014 date "2011-03-11" @default.
- W1566783014 modified "2023-10-17" @default.
- W1566783014 title "ESD Power Grid Design" @default.
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- W1566783014 doi "https://doi.org/10.1002/9781119991137.ch3" @default.
- W1566783014 hasPublicationYear "2011" @default.
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