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- W1567203094 startingPage "3188" @default.
- W1567203094 abstract "Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted." @default.
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- W1567203094 date "2005-11-01" @default.
- W1567203094 modified "2023-09-27" @default.
- W1567203094 title "Timing-Driven Global Routing with Efficient Buffer Insertion" @default.
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- W1567203094 doi "https://doi.org/10.1093/ietfec/e88-a.11.3188" @default.
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