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- W1567442757 abstract "This work describes a CMOS dual-modulus prescaler using double-edge-triggered (DET) D-flip-flops. This technique enables a frequency synthesizer to be divided by 64/64.5. Simulation results show that 35% reduction of power dissipation can be obtained. Using a 0.25mum process, a dual-modulus prescaler can operate at 1.8GHz while dissipating 5.525 mW power" @default.
- W1567442757 created "2016-06-24" @default.
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- W1567442757 date "2006-01-05" @default.
- W1567442757 modified "2023-09-26" @default.
- W1567442757 title "A Dual-Modulus Prescaler Using Double-Edge-Triggered D-Flip-Flops" @default.
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- W1567442757 doi "https://doi.org/10.1109/mwscas.2003.1562255" @default.
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