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- W1567509742 abstract "Montgomery multiplication normally spends over 90% of its execution time in inner loops executing some kind of multiply-and-add operations. The performance of these critical code sections can be greatly improved by customizing the processor’s instruction set for low-level arithmetic functions. In this paper, we investigate the potential of architectural enhancements for multiple-precision Montgomery multiplication according to the so-called Finely Integrated Product Scanning (FIPS) method. We present instruction set extensions to accelerate the FIPS inner loop operation based on the availability of a multiply/accumulate (MAC) unit with a wide accumulator. Finally, we estimate the execution time of a 1024-bit Montgomery multiplication on an extended MIPS32 core and discuss the impact of the multiplier latency." @default.
- W1567509742 created "2016-06-24" @default.
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- W1567509742 date "2003-01-01" @default.
- W1567509742 modified "2023-10-02" @default.
- W1567509742 title "Architectural Enhancements for Montgomery Multiplication on Embedded RISC Processors" @default.
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- W1567509742 doi "https://doi.org/10.1007/978-3-540-45203-4_32" @default.
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