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• W1567876860 abstract "A fine-grained reconfigurable architecture based on double gate technology is presented. The logic function operating on the first gate of a double gate (DG) transistor is reconfigured by altering the bias on its second gate. A compact reconfigurable cell is proposed that merges two stacked 3-state resonant tunneling devices and non-silicon transistors and hides the cost of reconfiguration by exploiting vertical integration. Each cell in the array can act as logic or interconnect, or both - contrasting with current FPGA structures in which logic and interconnect are built and configured largely as separate items. Simulation results for a SOI DG-MOSFET implementation is presented and two alternative non-silicon device technologies, metal-insulator-metal and carbon nanotube transistors, are briefly explored Of these, carbon nanotube devices appear to offer the highest current drive at the limit of scaling and will operate into the gigahertz range but then only within architectures that are locally connected." @default.
• W1567876860 created "2016-06-24" @default.
• W1567876860 creator A5061385879 @default.
• W1567876860 date "2003-10-01" @default.
• W1567876860 modified "2023-10-16" @default.
• W1567876860 title "A fine-grained reconfigurable logic array based on double gate transistors" @default.
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• W1567876860 doi "https://doi.org/10.1109/fpt.2002.1188690" @default.
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