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- W1567993624 abstract "As chips become faster, the need to test them at their intended speed of operation has been recognized. High-speed operation, together with the higher switching activity typically induced during test, can result in a die-thermal distribution significantly different from that achieved during normal operation. Differences in thermal map distribution between normal- and test-mode operations give rise to a non-uniform impact on the relative path delay within logic blocks. The impact of test-induced hot spots may artificially slow down non-critical paths or speed-up critical ones with respect to the clock making the whole die to fail (pass) delay testing for a good (bad) part. The non-uniform thermal-induced delay is especially important for clock circuitry, the most critical block, which is impacted even if exact zero-skew clock routing algorithms are adopted. In this work we analyze the impact of thermal map temperature changes on the clock delay identifying a new delay-fault mechanism. We propose a technique to minimize the impact of different test- and normal-mode thermal maps by making the clock tree speed independent of temperature gradients. This technique allows applying confidently delay test patterns to the die regardless of the thermal-map test-induced modification." @default.
- W1567993624 created "2016-06-24" @default.
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- W1567993624 date "2005-03-21" @default.
- W1567993624 modified "2023-10-01" @default.
- W1567993624 title "Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanism" @default.
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- W1567993624 doi "https://doi.org/10.1109/test.2004.1387402" @default.
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