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- W1568681143 abstract "The advance in fabrication technology hugely increases the number of available transistors on a single chip. It allows the industry to build the entire system on a single chip which was only realizable on a board in the past. On-chip System not only reduces the computer physical size, but also increases the computation performance because modules/cores/intellectual properties (IPs) are packed closely together. When simply increasing the clock frequency to increase the computer performance becomes harder because of the wire delay, putting more computation units on a single chip becomes a good alternative for improving computer performance. Building more cores on a chip in the future is expected. With many IPs on a chip, traditional bus is no longer able to provide enough bandwidth to support the communication between IPs. Providing a high performance on-chip network infrastructure for the IP communication becomes a key to high performance on-chip computation. This thesis focuses on an on-chip network supporting on-chip system. This thesis is composed of two main parts. In the first part, a high performance deadlock free dual-coded on-chip router using adaptive multicast routing is built. Compared with the traditional deterministic XY unicast router, this router can reduce both packet latency and energy consumption. In the second part, a co-processor placement algorithm for an on-chip system built from FPGAs with an on-chip network is proposed. The algorithm aims to place the communicating modules as close as possible. In addition, an algorithm for sharing a FPGA by multiple coprocessors and an algorithm for supporting polymorphic co-processor are proposed to increase on-chip FPGA system throughput." @default.
- W1568681143 created "2016-06-24" @default.
- W1568681143 creator A5010283949 @default.
- W1568681143 date "2018-08-10" @default.
- W1568681143 modified "2023-09-23" @default.
- W1568681143 title "A study of on-chip FPGA system with 2D mesh network" @default.
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- W1568681143 doi "https://doi.org/10.31274/etd-180810-2018" @default.
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