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• W156921408 abstract "Systems-on-Chip (SoCs) are considered an integral solu-tion for designing embedded systems, for targeting complexintensive parallel computation applications. As advances inSoC technology permit integration of increasing number ofhardware resources on a single chip, the targeted applicati ondomains such as software-den ed radio are become increas-ingly sophisticated. The fallout of this complexity is that thesystem design, particularly software design, does not evol veat the same pace as that of hardware leading to a signic antproductivity gap . Adaptivity and recong urability are alsocritical issues for SoCs which must be able to cope with enduser environment and requirements.An effective solution to SoC Co-design problem consists inraising the design abstraction levels. The important requi re-ment is to n d efc ient design methodologies that raise thedesign abstraction levels to reduce overall SoC complexity .A suitable control model is also required for managing thesystem adaptivity; it should be generic enough to be appliedto both software and hardware design aspects. While severalcontrol models exist, automata based control [1] are promis ingas they incorporate aspects of modularity present in compon entbased approaches for describing SoC in an incremental fashi onto build these complex systems.Once a suitable control model is chosen, implementation ofthese adaptive SoC systems can be carried out via FPGAs.These FPGAs are inherently recong urable in nature. Stateof the art FPGAs can change their functionality at runtime ,known as Partial Dynamic Recong uration (PDR) [2]. TheseFPGAs also support internal self dynamic recong uration, i nwhich an internal controller (a hardcore /softcore embeddedprocessor) manages the recong uration aspects.Finally the usage of concurrent high level design approachin development of real-time embedded systems is also in-creasing to address the compatibility issues related to SoCCo-design. High abstraction level SoC co-modeling designapproaches have been developed in this context, such asModel-Driven Engineering (MDE) [3] that specify the systemusing the UML graphical language. MDE enables high levelsystem modeling (of both software and hardware) with thepossibility of integrating heterogeneous components into thesystem. Usage of UML for system description increases thesystem comprehensibility. This allows designers to provid ehigh-level descriptions of the system that easily illustra tethe internal concepts (task/data parallelism, data depend enciesand hierarchy). These specic ations can be reused, modie dor extended due to their graphical nature. Finally Modeltransformations [4] can be carried out to generate executablemodels or source code from high level models.Gaspard [5] is an MDE-based SoC co-design frameworkthat uses the UML MARTE prol e [6] to model real-timeand embedded systems; and allows to move from high levelMARTE specic ations to different execution platforms suchas RTL synthesis in FPGAs [7]. It exploits the inherentparallelism included in repetitive constructions of hardwareelements or regular constructions such as application loop s.The applications targeted by Gaspard also focus on a specicapplication domain, that of data-parallel applications.In this paper we present a generic control semantics forexpressing partial recong urability in SoCs. The introduc edcontrol semantics are introduced in the MARTE standardand subsequently in Gaspard; and are specie d at an highabstraction level. Integration of this control allows to fo cuson FPGA synthesis and is specially oriented towards PDR.The goal is to specify part of the recong urable system at ahigh abstraction level: notably the recong urable region a ndthe recong uration controller in a dynamically recong ura bleFPGA. Afterwards, using model transformations, the gap be-tween high level specic ations and low implementation deta ilscan be bridged to automatically generate the code required f orthe creation of bitstream(s) for n al FPGA implementation.Finally we present a case study illustrating the modelingand n al implementation of a dynamically recong urable keyintegral part of an anti-collision radar detection system. Thispart is based on delay estimation using a correlation algori thm.This part is modeled at an high abstraction level using theMARTE prol e in the Gaspard framework. Afterwards usingthe model transformations present in our design o w, we havegenerated the necessary RTL level code for synthesis on atarget FPGA using commercial tools. It should be observedthat the n al code generation from the high level modelsusually is carried out in a few seconds resulting in a hugesave in the overall system conception development time.The rest of this paper is organized as follows. Relatedworks are detailed in section II. An overview of the MDE-based Gaspard framework is provided in section III. SectionIV describes the control model in Gaspard, while SectionV presents our case study. Finally section VIII gives theconclusion of the paper." @default.
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• W156921408 date "2009-10-12" @default.
• W156921408 modified "2023-09-23" @default.
• W156921408 title "MARTE based design flow for Partially Reconfigurable Systems-on-Chips" @default.
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