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• W1569339104 abstract "Part 1 Compilation for parallelism: decomposed software pipelining - a new approach to exploit instruction level parallelism for loop programs, J. Wang and C. Eisenbeis software pipelining - petri net pacemaker, V.H. Allan et al efficient execution of doacross loops on distributed memory systems, A. Zaafrani and M.R. Ito balancing fine- and medium-grained parallelism in scheduling loops for the XIMD architecture, C.J. Newburn et al a new loop partition method-clustering, S.Y. Tseng et al flow-sensitive inter-procedural analysis method for parallelization, T. Iitsuka code generation for multi-threaded architectures from dataflow graphs, S. Murer and P. Farber the initial performance of a bottom-up clustering algorithm for dataflow graphs, W.A. Najjar et al. Part 2 Architectures: synchronization and parallelism control in the BARDE dataflow processor, H. Seebauer and J. Siemers the instruction set architecture of the inference processor UNIRED II, K. Shimada et al a functional data-flow architecture dedicated to real-time image processing, J. Serot et al DART - a data-driven processor architecture for real-time computing, W.G. Farquhar and P. Evripidou two fundamental limits on dataflow multiprocessing, D.E. Culler et al the realities of parallel processing and dataflow's role in it - a NASA HPCC perspective, T.L. Sterling and M.J. MacDonald. Part 3 Communication issues: integrated network barriers for d-dimensional meshes, J.A. Solworth and J. Stamatopoulos parallel dimension permutations on star graph, S. Latifi on the effectiveness of interleaved memories for binary trees, R.V. Boppana. Part 4 VLIW processors: contribution of compilation techniques to the synthesis of dedicated VLIW architectures, G. Menez et al selective scheduling framework for speculative operations in VLIW and superscalar processors, S.M. Moon et al URSA - a Unified ReSource Allocator for registers and functional units in VLIW architectures, D.A. Berson et al. Part 5 Experiences in parallel computing: data flow computing and the conjugate gradient method, N. Rubin results of parallel implementations of the selection problem using SISAL, M. Daumas and P. Evripidou a parallel implementation of the travelling salesman problem on a sequent symmetry multiprocessor, A. Sohn. Part 6 Language issues: exploring the stream data type in SISAL and other languages, A.L. Wendelborn and H. Garsden multidimensional streams rooted in dataflow, E.A. Lee. Part 7 Compiling practice: high level compiling for low level machines, C. O'Donnell modelling instruction-level parallelism for software pipelining, A. Adl-Tabatabai et al." @default.
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• W1569339104 title "Architectures and compilation techniques for fine and medium grain parallelism : proceedings of the IFIP WG 10.3 Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, Florida, USA, 20-22 January 1993" @default.
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