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- W1569348616 abstract "The adoption of the System-on-Chip design paradigm creates new challenges for designers and test engineers. In this chapter a high-level test generation approach is presented, which is able to produce high-quality vectors that can be fruitfully exploited for test and validation purposes of both the hardware and software components of System-on-Chip designs. Experimental results are reported showing that our high-level test generation algorithm produces high-quality vectors in terms of stuck-at fault coverage for hardware components and code mutants for software components. The vectors produced can also be exploited for validation purposes, as the results gathered while validating a processor core suggest." @default.
- W1569348616 created "2016-06-24" @default.
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- W1569348616 date "2005-01-01" @default.
- W1569348616 modified "2023-09-26" @default.
- W1569348616 title "Test Generation: A Heuristic Approach" @default.
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- W1569348616 doi "https://doi.org/10.1007/1-84628-145-8_4" @default.
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