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- W1569442065 abstract "Computational energy versus computational precision represents a critical implementation-level tradeoff facing embedded DSP systems. Focusing on multiply-accumulate (MAC) hardware, which is used extensively in DSP implementations (e.g., FIR filtering), this paper proposes an approach that exploits floating-point representation of multipliers to enable optimization of their quantization error. The approach introduces a parameter α for coefficient scaling, and optimizes α to minimize the output error. Applied to FIR filters with coefficient representation of 6 bits, the approach reduces the quantization error by 37×, compared to traditional, linear-quantized fixed-point coefficient representation and by 28×, compared to unoptimized floating-point coefficient representation. Further, the energy and hardware gate-count of a MAC unit is reduced by 1.4× and 1.2×, respectively, compared to an implementation based on fixed-point representation." @default.
- W1569442065 created "2016-06-24" @default.
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- W1569442065 date "2015-04-01" @default.
- W1569442065 modified "2023-09-26" @default.
- W1569442065 title "Reducing quantization error in low-energy FIR filter accelerators" @default.
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- W1569442065 doi "https://doi.org/10.1109/icassp.2015.7178126" @default.
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