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- W1569461127 abstract "Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are mostly based on edge triggered flip-flops. In this paper, we demonstrate the advantages of using level sensitive latches in terms of both latency and area cost. The input-output timing coupling and the strict short path constraint for latches demand additional design elaborations compared with flip-flops. New approaches are proposed in this work to solve these difficulties so that the advantages of latches can be fully utilized. In particular, a deferred delay padding technique is developed to correct short path violations with the minimal extra cost. These techniques are integrated with a dynamic programming based concurrent synchronous element and repeater insertion framework. Experimental results confirm the advantages of using latches as well as effectiveness of our algorithms." @default.
- W1569461127 created "2016-06-24" @default.
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- W1569461127 date "2005-02-22" @default.
- W1569461127 modified "2023-10-03" @default.
- W1569461127 title "Exploiting level sensitive latches in wire pipelining" @default.
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- W1569461127 doi "https://doi.org/10.1109/iccad.2004.1382587" @default.
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