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- W1569705806 abstract "The conventional synchronous design approach is not suitable for implementing self-timed circuits on FPGAs. When design tools try to meet synchronous circuits timing constraints, they can violate self-timed setup timing constraints. This paper proposes a new methodology for implementing self-timed circuits in modern FPGAs using the Xilinx Hierarchical Design flow and a convenient architecture of a configurable delay element. Reported simulation results, in accordance with static timing analysis, show that the self-timed timing constraints are satisfied using our design methodology." @default.
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- W1569705806 date "2015-06-01" @default.
- W1569705806 modified "2023-09-25" @default.
- W1569705806 title "Self-timed circuits FPGA implementation flow" @default.
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- W1569705806 doi "https://doi.org/10.1109/newcas.2015.7182063" @default.
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