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• W1569741251 abstract "The fundamental model of memory requires each read to an address to return the most recent value written to the same address. This model becomes a consistency requirement for parallel shared memory machines, and is taken as a necessary property for correct algorithm execution. In Distributed Shared Memory (DSM) systems the presence of processor memory caches means that the processors may develop historical and therefore different views of the distributed memory. The paper examines the relationship between synchronisation and consistency, proposes that synchronisation should enforce consistency, and examines the consequences using barriers as an example. A typical shared memory MIMD program is shown to execute correctly without normal consistency, and the experiment suggests that the relationship between synchronisation and consistency bears further investigation." @default.
• W1569741251 created "2016-06-24" @default.
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• W1569741251 date "1993-01-01" @default.
• W1569741251 modified "2023-10-07" @default.
• W1569741251 title "Barrier semantics in very weak memory" @default.
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• W1569741251 doi "https://doi.org/10.1007/3-540-56891-3_70" @default.
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