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- W1570605631 abstract "System-on-chip (SoC) design is facing increasing difficulties in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over the conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. The combination of these two technologies therefore could be an optimal solution for the interconnection of SoC. In this paper, we focus on the implementation of packet-switch with asynchronous technology. The results of experiments run to evaluate several aspects of the packet-switch implementation are presented." @default.
- W1570605631 created "2016-06-24" @default.
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- W1570605631 date "2005-06-01" @default.
- W1570605631 modified "2023-09-24" @default.
- W1570605631 title "Asynchronous packet-switch for SoC" @default.
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- W1570605631 doi "https://doi.org/10.1109/icm.2004.1434580" @default.
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